1. Field of the Invention
The present invention relates to a method and apparatus for data transmission, and more particularly relates to a method and apparatus for transmitting registered data onto a PCI bus, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity.
2. Description of the Related Art
Computer systems commonly employ one or more peripheral buses that enable communications among a variety of devices. The communications between these devices, which are so-called xe2x80x9cagentsxe2x80x9d, generally are performed according to protocols. One of the protocols is the Peripheral Component Interconnect (PCI) published bus specification, which allows data communication bandwidth up to 266 megabytes per second when the clock frequency is 66 MHz.
Typically, there are many agents coupled to the PCI bus. A data transfer on a PCI bus is performed when one requesting agent issues a bus transaction to another receiving agent. The requesting agent is referred to as the xe2x80x9cmasterxe2x80x9d agent, and the receiving agent is referred to as the xe2x80x9ctargetxe2x80x9d agent. The master agent drives address/command to a target agent and, if the command is xe2x80x9cwritexe2x80x9d, further drives a set of data following the address/command. Then, the target agent decodes the address and accepts the data if the command is xe2x80x9cwritexe2x80x9d, or returns some data if the command is xe2x80x9creadxe2x80x9d. A bus transaction thus consists of an address phase followed by one or more data phases.
FIG. 1 is a functional block-diagram illustrating the output control logic of a conventional master agent coupled to a PCI bus 100. Note that the PCI bus 100 defined in the specification has more than 47 pins, but in this figure, only the AD bus AD[31:0] 101 are specified for clarity. The internal control signals, current phase data pointer 105, current phase address pointer 106 and address phase selector 107 are internal state signals of the agent. The current phase data pointer 105 and current phase address pointer 106 are two pointers controlled by the ongoing transaction to switch the data and address signals stored in the buffers 113 and 112, respectively. The address phase selector 107 is used to select the address phase or the data phase. A multiplexer 111 and an I/O buffer 110 are used to transmit signals onto the PCI bus 100. Note that the actual implementation of the data buffer and the address buffer can be any form.
PCI data transfers are controlled by three signals, including FRAME#, IRDY# and TRDY#. The signal FRAME# is driven by the master to indicate the beginning and the end of a transaction. The signal IRDY# is driven by the master to indicate that the master is ready to transfer data. And the signal TRDY# is driven by the target to indicate that the target is ready to transfer data. The interface is in the Idle state if both the FRAME# and IRDY# signals are de-asserted. When the FRAME# signal is asserted, it is referred to as the address phase, and the address/bus command code are transferred on the first clock edge data is then transferred during the following data phase while both the IRDY# and TRDY# are asserted. As the master finishes transferring the final data, the FRAME# signal is then de-asserted. After the target agent completes transferring the final data, the IRDT# signal is also de-asserted and the interface returns to the Idle state.
FIG. 2 is a timing diagram of the operation of the conventional master agent illustrated in FIG. 1. The upper half of this diagram shows the waveforms of the internal signals of the master agent, and the lower half shows the waveforms of outgoing signals driven onto the PCI bus 100 by the master agent. In the third clock cycle, the address phase selector 107 chooses the address Aj from address buffer 112, and drives the address signal onto PCI bus 100 after some delay D2 produced by the multiplexer 111 and the I/O buffer 110. In the next clock cycle, the address phase selector 107 is de-asserted and the multiplexer 111 selects the data Di, which comes from the data buffer 113 and is pointed by current phase data pointer 105 (with index i). Since no data transfer occurs in this clock cycle, Di is kept on driving onto PCI bus 100 in the sixth clock cycle. After the sixth clock cycle, while both TRDY# and IRDY# are asserted, the index i of the current phase data pointer 105 will shift to i+1. Besides the output delay produced by the multiplexer 111 and the I/O buffer 110, data phase switching from Di to Di+1 also results in some delay.
Thus, the master agent as shown in FIG. 1 will induce lots of delays, such as D1 and D2, before driving AD signals onto the PCI bus. This delay will reduce the time budget of the target agent that receives the signals on the same PCI bus. When the clock cycle becomes shorter and shorter, it would be difficult for the target agent to manipulate the signals well. For example, when the clock frequency is up to 66 MHz and a cycle time is reduced to 15 ns, it is frustrated to handle the signals in such a short or even a shorter time period.
In order to solve the delay issue described above, another circuit with two-level pipelined stages is illustrated in FIG. 3. FIG. 3 shows a functional block diagram illustrating the output control logic of a conventional pipelined agent. In this circuit structure, output signals are registered before transmitting onto the PCI bus 300, and data prepared by the 1R1W (one read ports and one write port) data buffer 310 is done one clock before the signal is transmitted, which relates to a next data 321 preparation in the agent. Obviously, this circuit must employee another pipelined stage (register) for storing the initial data phase before the first data transfer occurs on the PCI bus 300. As shown in FIG. 3, the circuit employees two multiplexers 311 and 312, and flip-flop 313 and 314 to sustain the initial data until a successful data transfer occurs. However, this circuit illustrated in FIG. 3 is much complex.
It would be desirable to provide a simple method and apparatus in which the agent can output signals with a higher speed without greatly increasing the circuit complexity, thus can conform with the timing requirements defined in the PCI specification.
An object of the present invention is to provide a method and apparatus for transmitting registered data onto a PCI bus, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit complexity.
An apparatus according to the present invention comprises a data buffer for storing a plurality of registered data and outputting a current data signal and a next data signal according to a current phase data pointer and a next phase data pointer, respectively. The apparatus further comprises an address buffer for storing address signals and outputting current address signal according to a current phase address pointer. Besides, the apparatus also comprises a first multiplexer coupled to the data buffer and the address buffer for selecting the current data signal or the current address signal according to an address phase Select signal. A OR logic gate is employed for receiving an IRDY# signal and a TRDY# signal from the PCI Bus and outputting a data Transfer Select signal. A second multiplexer couples to the data buffer and the first multiplexer for selecting the output of the first multiplexer or the next data signal according to the data Transfer Select signal. A flip-flop couples to the second multiplexer for toggling the output signal of the second multiplexer to the PCI Bus according to a reference clock.
The apparatus further comprises a first I/O buffer coupled to the flip-flop for transferring the output signal of the flip-flop to the PCI Bus, a second I/O buffer coupled to the logic gate for transferring the IRDY# signal from the PCI Bus to the logic gate, and a third I/O buffer coupled to the logic gate for transferring the TRDY # signal from the PCI Bus to the logic gate.
The method according to the present invention comprises the steps of:
a) output a current data signal and a next data signal by a data buffer to a first multiplexer and a second multiplexer, respectively;
b) output an address signal by an address buffer to the first multiplexer;
c) select the current data signal or the address signal by the first multiplexer according to an address phase Select signal;
d) select the next data signal or the output signal of the first multiplexer by the second multiplexer according to a data Transfer Select signal, which is the output signal of a logic gate with IRDY# and TRDY# signals as inputs; and
e) send the output signal of the second multiplexer to the PCI bus by a flip-flop.